Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference A-7
Blackfin Processor Core MMR Assignments
Interrupt Controller Registers
Table A-3 lists the MMR assignments for the Interrupt Controller regis-
ters (0xFFE0 2000–0xFFE0 210C).
0xFFE0 1238 ICPLB_DATA14 “ICPLB Data Registers (ICPLB_DATAx)” on
page 6-67
0xFFE0 123C ICPLB_DATA15 “ICPLB Data Registers (ICPLB_DATAx)” on
page 6-67
0xFFE0 1300 ITEST_COMMAND “Instruction Test Command Register
(ITEST_COMMAND)” on page 6-27
0XFFE0 1400 ITEST_DATA0 “Instruction Test Data 0 Register
(ITEST_DATA0)” on page 6-29
0XFFE0 1404 ITEST_DATA1 “Instruction Test Data 1 Register
(ITEST_DATA1)” on page 6-28
Table A-3. Interrupt Controller Registers
Memory-Mapped
Address Register Name See Section
0xFFE0 2000 EVT0
(EMU) “Core Event Vector Table” on page 4-35
0xFFE0 2004 EVT1
(RST) “Core Event Vector Table” on page 4-35
0xFFE0 2008 EVT2
(NMI) “Core Event Vector Table” on page 4-35
0xFFE0 200C EVT3
(EVX) “Core Event Vector Table” on page 4-35
0xFFE0 2010 EVT4 “Core Event Vector Table” on page 4-35
Table A-2. L1 Instruction Memory Controller Registers (Cont’d)
Memory- Mapped
Address Register Name See Section