Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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General-Purpose Timer Registers
16-8 ADSP-BF535 Blackfin Processor Hardware Reference
extra
SSYNC
instruction may be inserted. In External Event Counter mode
(EXT_CLK), reset the
IRQx
bit in the
TIMERx_STATUS
register at the very
beginning of the ISR to avoid missing any timer events.
Before enabling a timer, always program the corresponding Timer Config-
uration register (
TIMERx_CONFIG
). This register defines the timer operating
mode, the polarity of the
TMRx
pin, and the timer interrupt behavior. Do
not alter the operating mode while the timer is running.
Figure 16-4 describes the Timer Configuration registers.
The
UARTy_RX_SEL
bit applies to WDTH_CAP mode only. It is intended
for UART autobaud detection. If this bit is set, the
UARTy RX
pin is cap-
tured instead of the
TMRx
pin, Timer 0 alternatively captures
UART0
, Timer
1 alternatively captures
UART1
, and Timer 2 alternatively captures
UART1
.
Figure 16-4. Timer Configuration Registers
Table 16-3. Timer Configuration Register MMR Assignments
Register Name Memory-Mapped Address
TIMER0_CONFIG 0xFFC0 2002
TIMER1_CONFIG 0xFFC0 2012
TIMER2_CONFIG 0xFFC0 2022
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0
MODE_FIELD[1:0]
Reset = 0x0000 0
Timer Configuration Registers (TIMERx_CONFIG)
0 - Negative action pulse
1 - Positive action pulse
0 - Count to end of width
1 - Count to end of period
0 - Disable interrupt request
1 - Enable interrupt request
0 - TMR_PIN selected
1 - UARTy RX selected
00 - Reset state
01 - PWM_OUT mode
10 - WDTH_CAP mode
11 - EXT_CLK mode
PULSE_HI
PERIOD_CNT (Period Count)
IRQ_ENA (Interrupt Request Enable)
UARTy_RX_SEL (UARTy Input Select)
For MMR
assignments, see
Table 16-3 .