Event Handling
1-10
ADSP-BF535 Blackfin Processor Hardware Reference
I/O Memory Space
Blackfins do not define a separate I/O space. All resources are mapped
through the flat 32-bit address space. On-chip I/O devices have their con-
trol registers mapped into memory-mapped registers (MMRs) at addresses
near the top of the 4 Gbyte address space. These are separated into two
smaller blocks: one that contains the control MMRs for all CPU core
functions and the other contains the registers needed for setup and control
of the on-chip peripherals outside of the CPU core. The core MMRs are
accessible only by the core and only in Supervisor mode. They appear as
reserved space by on-chip peripherals, as well as external devices accessing
resources through the PCI bus. The system MMRs are accessible by the
core in Supervisor mode and can be mapped as either visible or reserved to
other devices, depending on the system protection model.
Event Handling
The event controller on the ADSP-BF535 processor handles all asynchro-
nous and synchronous events to the processor. The ADSP-BF535
processor event handling supports both nesting and prioritization. Nest-
ing allows multiple event service routines to be active simultaneously.
Prioritization ensures that servicing a higher priority event takes prece-
dence over servicing a lower priority event. The controller provides
support for five different types of events:
• Emulation
• Causes the processor to enter Emulation mode, allowing command
and control of the processor via the JTAG interface.
• Reset
• Resets the processor.
• Nonmaskable Interrupt (NMI)
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...