Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 777 / 1022

ADSP-BF535 Blackfin Processor Hardware Reference 18-53
External Bus Interface Unit
SDRAM Control Status Register (EBIU_SDSTAT)
The SDRAM Control Status register, shown in Figure 18-16 , provides
information on the state of the SDC. This information can be used to
determine when it is safe to alter SDC control parameters or as a debug
aid. The error bits of this register are sticky. Once an error bit has been
set, software must explicitly write a 1 to the bit to clear it.
16 64 9
Not Supported - Reserved
16 64 8
16 32 11
16 32 10 2 IA[24:13] IA[12:11] IA[10:1] IA[0] 64 4 4
128 8 2
16 32 9 1 IA[24:12] IA[11:10] IA[9:1] IA[0] 256 16 1
16 32 8
Not Supported - Reserved
16 16 11
16 16 10
16 16 9 1 IA[23:12] IA[11:10] IA[9:1] IA[0] 64 8 2
128 16 1
16 16 8 Not Supported - Reserved
Table 18-5. Internal Address Mapping (Cont’d)
Bank
Width
Bits Bank
Size
Mbyte Col
Addr
Width
(CAW Page
Size
kbyte Row
Address Bank
Address Page SDRAM Config
Column
Address Byte
Address Size
Mbit Width
Bits Num
Chips