Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-28 ADSP-BF535 Blackfin Processor Hardware Reference
SDRAM Controller (SDC)
The SDRAM Controller (SDC) enables the ADSP-BF535 processor to
transfer data to and from Synchronous DRAM (SDRAM). The
ADSP-BF535 processor supports a glueless interface with up to four banks
of standard SDRAMs of 64 Mbit, 128 Mbit, 256 Mbit, and 512 Mbit
with configurations x4, x8, and x16. Each bank supports up to 128
MByte, with a maximum total capacity of 512 MBytes (MB) of SDRAM.
The interface can also support DIMMs and includes timing options to
support additional buffers between the ADSP-BF535 processor and
SDRAM, to handle the capacitive loads of large memory arrays.
All inputs are sampled and all outputs are valid on the rising edge of the
SDRAM clock output
SCLK[0]
(or
SCLK[1],
which has the same timing).
The SDRAM interface is able to connect to as many as four external mem-
ory banks of SDRAM. All banks share the same SDRAM timing
parameters.

Do not confuse the “SDRAM internal banks” which are internal to
the SDRAM and are selected with the bank address, with the four
“SDRAM banks,” or “external banks,” that are enabled by the
SMS[3:0]
pins.
The EBIU SDC provides a glueless interface with standard SDRAMs. The
ADSP-BF535 processor’s SDRAM controller:
• Supports SDRAMs of 64 Mbit, 128 Mbit, 256 Mbit, and
512 Mbit with configurations of x4, x8, and x16.
• Supports up to two x64 DIMM modules, or up to four x32 DIMM
modules.
• Supports up to 512 MB total array size with 128 MB of SDRAM
on each of the four external SDRAM banks.