Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Index
I-30 ADSP-BF535 Blackfin Processor Hardware Reference
reset (continued)
effect on memory configuration, 6-12
effect on PLL Control register pins, 8-7
Hardware, 3-12 , 8-14
hardware, 3-13
PCI, 13-16
peripheral clock enablement, 8-23
System Software, 3-12 , 3-14
timing of pins, 19-5
USB signalling, 14-61
Watchdog Timer, 3-13 , 3-14
reset initialization sequence
programming for interrupts, 4-28
reset interrupt (RST), 4-36
RESET signal, 3-11
Reset state, 3-6 , 3-10
reset vector, 4-37
Reset Vector Addresses (table), 4-37
resources accessible from EMB, 7-19
retries, PCI, 13-8
RETS register, 4-11
return
from emulation (RTE) instruction, 3-4 ,
4-10
from exception (RTX) instruction, 3-4 ,
4-10
from interrupt (RTI) instruction, 3-4 ,
4-10
from non-maskable interrupt (RTN)
instruction, 3-4 , 4-10
from subroutine (RTS) instruction, 4-10
return address, 4-2 , 4-9
Return Address registers, 4-4
return instructions, 4-10
RETx register, 3-5
revision ID, PCI, 13-34
RND_MOD bit, 2-18 , 2-20
ROM, 1-8 , 1-12 , 18-1
rounding
biased, 2-18 , 2-20
convergent, 2-18
instructions, 2-18 , 2-21
unbiased, 2-18
router, 7-5
routing, 7-6
row address, 18-51
RST
core event, 4-19
reset interrupt, 4-36
RTC, 1-2 , 1-15 , 17-1
alarm clock features, 17-2
counters, 17-1
digital watch features, 17-1
prescaler, 17-1
programming model, 17-2
stopwatch function, 17-2
timing and clock inputs, 8-2
RTC Alarm register (RTC_ALARM),
17-11
RTC_ALARM (RTC Alarm register),
17-11
RTC Enable register (RTC_FAST), 17-12
RTC_FAST (RTC Enable register), 17-12
RTC_ICTL (RTC Interrupt Control
register), 17-8
RTC Interrupt Control register
(RTC_ICTL), 17-8
RTC Interrupt Status register
(RTC_ISTAT), 17-9
RTC_ISTAT (RTC Interrupt Status
register), 17-9
RTC_STAT (RTC Status register), 17-7
RTC Status register (RTC_STAT), 17-7
RTC Stopwatch Count register
(RTC_SWCNT), 17-10
RTC_SWCNT (RTC Stopwatch Count
register), 17-10