Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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10-2 ADSP-BF535 Blackfin Processor Hardware Reference
The ADSP-BF535 SPI is an industry-standard synchronous serial link that
supports communication with multiple SPI compatible devices. The SPI
peripheral is a synchronous, 4-wire interface consisting of two data pins
(
MOSI
and
MISO
), one device select pin (
SPISS
), and a gated clock pin (
SCK
).
The ADSP-BF535 SPI supports these features:
• Full duplex operation
• Master-slave mode multimaster environment
• Open drain outputs
• Programmable baud rates, clock polarities, and phases
• Slave operations with another master SPI device
The SPI can operate in a multimaster environment by interfacing with
several other devices, acting as either a master device or a slave device. In a
multimaster environment, the SPI interface uses open drain outputs to
avoid data bus contention.
Figure 10-1 provides a block diagram of the ADSP-BF535 SPI. The inter-
face is essentially a shift register that serially transmits and receives data
bits, one bit a time at the
SCK
rate, to and from other SPI devices. SPI data
is transmitted and received at the same time through the use of a shift reg-
ister. When an SPI transfer occurs, data is simultaneously transmitted
(shifted serially out of the shift register) as new data is received (shifted
serially into the other end of the same shift register). The
SCK
synchronizes
the shifting and sampling of the data on the two serial data pins.