Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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RTC Programming Model
17-4 ADSP-BF535 Blackfin Processor Hardware Reference
Writes to clear bits in
RTC_ISTAT
take effect immediately.
The single active bit of the RTC Enable register (
RTC_FAST
) is set using a
synchronization path. Clearing the bit is accomplished with a clear signal
that is synchronized by the 32.768 kHz clock. This faster synchronization
allows the module to be put into high-speed mode (bypassing the pres-
caler) without waiting the 1 to 2 seconds for the write to complete if the
module is already running with the prescaler enabled. The first positive
edge of the 1 Hz clock occurs 2 to 3 cycles of the 32.768 kHz clock after
the prescaler is enabled.
Note the clear path does not clear the synchronization path for the bit that
is set. Setting, then immediately clearing, the Prescaler Enable bit could
result in its being set.

Clear all flags at power-up and when setting the RTC Status regis-
ter (
RTC_STAT
), the RTC Alarm register (
RTC_ALARM
), or the RTC
Stopwatch Count register (
RTC_SWCNT
). Wait for the write to com-
plete for all of these registers before clearing the flags and enabling
the Alarm interrupt, Day Alarm interrupt, or Stopwatch interrupt.
The unknown values in the registers at power-up can cause interrupts to
occur before the correct value is written into each of the registers. By
catching the slow clock edge, the write to
RTC_STAT
can occur a full second
before the write to
RTC_ALARM
. This would cause an extra second of delay
between the validity of
RTC_STAT
and
RTC_ALARM
, if the value of the
RTC_ALARM
out of reset is the same as the value written to
RTC_STAT
. Wait
for the writes to complete on these registers before using the flags and
interrupts associated with their values.