Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference B-23
System MMR Assignments
SPI0 Controller Registers
Table B-12 lists the MMR assignments for the SPI0 Controller registers
(0xFFC0 3000–0xFFC0 33FF).
0xFFC0 2F06 SPORT1_START_ADDR_LO_TX “SPORTx Transmit DMA Start
Address Low
(SPORTx_START_ADDR_LO_TX)
Registers” on page 11-44
0xFFC0 2F08 SPORT1_COUNT_TX “SPORTx Transmit DMA Count
(SPORTx_COUNT_TX) Registers”
on page 11-45
0xFFC0 2F0A SPORT1_NEXT_DESCR_TX “SPORTx Transmit DMA Next
Descriptor Pointer
(SPORTx_NEXT_DESCR_TX)
Registers” on page 11-45
0xFFC0 2F0C SPORT1_DESCR_RDY_TX “SPORTx Transmit DMA Descriptor
Ready (SPORTx_DESCR_RDY_TX)
Registers” on page 11-46
0xFFC0 2F0E SPORT1_IRQSTAT_TX “SPORTx Transmit DMA IRQ Sta-
tus (SPORTx_IRQSTAT_TX) Regis-
ters” on page 11-47
Table B-12. SPI0 Controller Registers
Memory-Mapped
Address Register Name See Section
0xFFC0 3000 SPI0_CTL “SPIx Control Register (SPIx_CTL)” on
page 10-8
0xFFC0 3002 SPI0_FLG “SPIx Flag Register (SPIx_FLG)” on
page 10-10
Table B-11. SPORT1 Controller Registers (Cont’d)
Memory-Mapped
Address Register Name See Section