Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 350 / 1022

Dynamic Power Management Controller
8-18 ADSP-BF535 Blackfin Processor Hardware Reference
Listing 8-1. PLL Programming Sequence
CLI Rn; /* disable interrupts, copy IMASK to Rn */
IDLE; /* source NOPs into pipeline, and enter idled state upon
SSYNC */
SSYNC; /* drain pipeline, enter idled state */
STI Rn; /* re-enable interrupts after wakeup, restore IMASK
from Rn */
The first three instructions in the sequence (
CLI
,
IDLE
, and
SSYNC
) take the
core to an idled state with interrupts disabled; the interrupt mask (
IMASK
)
is saved to the
Rn
register, and the instruction pipeline is halted. The PLL
state machine then loads the
PLL_CTL
register changes into the PLL.
If the
PLL_CTL
register changes include a new
CLKIN
to
CCLK
multiplier or
the changes reapply power to the PLL, the PLL needs to relock. To relock,
the PLL lock counter is first cleared, then begins incrementing, once per
SCLK
cycle. After the PLL lock counter reaches the value programmed into
the PLL Lock Count register (
PLL_LOCKCNT
), the PLL sets the
PLL_LOCKED
bit in the PLL Status register (
PLL_STAT
).
Depending on how the
PLL_CTL
register is programmed, the processor
proceeds in one of four ways:
• If the
PLL_CTL
register is programmed to enter either the Active or
Full On operating mode, the processor waits for a wake-up signal,
then continues with the
STI
instruction in the sequence, as
described in “PLL Programming Sequence Continues” on
page 8-19 .
• The wake-up signal is an interrupt generated by a peripheral,
watchdog or other timer, RTC, or other source. For more informa-
tion about events that cause the processor to wake-up from being
idled, see
“System Interrupt Wakeup-Enable Register (SIC_IWR)”
on page 4-24 .