Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-17
Memory
L1 Instruction Cache
The L1 Instruction Memory may also be configured as a flexible, 4-Way
set associative instruction cache. To improve the average access latency for
critical code sections, each Way of the cache can be locked independently.
When the memory is configured as cache, it cannot be accessed directly.
When cache is enabled, memory pages must be defined with Cacheability
Protection Lookaside Buffers (CPLBs). When CPLBs are enabled, any
memory location that is accessed must have an associated page definition
available, or an exception will be generated. CPLBs are described in
“Memory Protection and Properties” on page 6-56 .
Figure 6-6 shows the overall Blackfin processor instruction cache
organization.
Cache Lines
As shown in Figure 6-6 , the cache consists of a collection of cache lines.
Each cache line is made up of a tag component and a data component:
• The tag component incorporates a 20-bit address tag, least recently
used (LRU) bits, and a Valid bit.
• The data component is made up of four 64-bit words of instruction
data.
The tag and data components of cache lines are stored in the tag and data
memory arrays, respectively.
The address tag consists of the upper 18 bits plus bits 11 and 10 of the
physical address. Bits 12 and 13 of the physical address are not part of the
address tag. Instead, these bits are used to identify the 4 KB memory
sub-bank targeted for the access.
The LRU bits are part of an LRU algorithm used to determine which
cache line should be replaced if a cache miss occurs.