Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Barrel Shifter (Shifter)
2-44 ADSP-BF535 Blackfin Processor Hardware Reference
In this instruction, the 40-bit accumulator is packed into a 16-bit half reg-
ister. The result from MAC1 must be transferred to a high half of a
destination register and the result from MAC0 must be transferred to the
low half of the same destination register.
The operand type determines the correct bits to extract from the accumu-
lator and deposit in the 16-bit destination register. See
“Multiply Without
Accumulate” on page 2-40 .
R3 = ( A1 += R1.H * R2.L ), R2=( A0 += R1.L * R2.L ) ;
In this instruction, the 40-bit accumulators are packed into two 32-bit
registers. The registers must be register pairs (
R[1:0]
;
R[3:2] ; R[5:4]
; R[7:6]
)
R3.H = ( A1 += R1.H * R2.L ), A0 += R1.L * R2.L ;
This instruction is an example of one accumulator—but not the other—
being transferred to a register. Either a 16- or 32-bit register may be speci-
fied as the destination register.
Barrel Shifter (Shifter)
The shifter provides bitwise shifting functions for 16- or 32-bit inputs,
yielding a 16-, 32-, or 40-bit output. These functions include arithmetic
shift, logical shift, rotate, and various bit-test, set, pack, unpack and expo-
nent-detection functions. These shift functions can be combined to
implement numerical format control, including full floating-point
representation.
Shifter Operations
The shifter instructions (
>>>
,
>>
,
ASHIFT
,
LSHIFT
,
ROT
) can be used various
ways, depending on the underlying arithmetic requirements.
ASHIFT
and
>>>
represents the arithmetic shift.
LSHIFT
and
>>
represent the logical
shift.