Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-81
External Bus Interface Unit
SDRAM Performance
Table 18-19 lists the data throughput rates for the core, DMA, or PCI
read/write accesses to 32-bit wide SDRAM. For this example, assume all
cycles are
SCLK
cycles and the following
SCLK
frequency and SDRAM
parameters are used:
•
SCLK
frequency = 133 MHz
• CAS latency = 2 cycles (
CL = 2
)
• No SDRAM buffering (
EBUFE = 0
)
• RAS precharge (t
RP
) = 2 cycles (
TRP = 2
)
• RAS to CAS delay (t
RCD
) = 2 cycles (
TRCD = 2
)
• Active command time (t
RAS
) = 5 cycles (
TRAS = 5
)