Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory DMA Controller Registers
B-26 ADSP-BF535 Blackfin Processor Hardware Reference
Memory DMA Controller Registers
Table B-14 lists the MMR assignments for the Memory DMA Controller
registers (0xFFC0 3800–0xFFC0 3BFF).
0xFFC0 3608 SPI1_COUNT “SPIx DMA Count Register
(SPIx_COUNT)” on page 10-23
0xFFC0 360A SPI1_NEXT_DESCR “SPIx DMA Next Descriptor Pointer Register
(SPIx_NEXT_DESCR)” on page 10-24
0xFFC0 360C SPI1_DESCR_RDY “SPIx DMA Descriptor Ready Register
(SPIx_DESCR_RDY)” on page 10-25
0xFFC0 360E SPI1_DMA_INT “SPIx DMA Interrupt Register
(SPIx_DMA_INT)” on page 10-26
Table B-14. Memory DMA Controller Registers
Memory-Mapped
Address Register Name See Section
0xFFC0 3800 MDD_DCP “Destination Memory DMA Current
Descriptor Pointer Register (MDD_DCP)”
on page 9-37
0xFFC0 3802 MDD_DCFG “Destination Memory DMA Configuration
Register (MDD_DCFG)” on page 9-33
0xFFC0 3804 MDD_DSAH “Destination Memory DMA Start Address
Registers (MDD_DSAH, MDD_DSAL)” on
page 9-35
0xFFC0 3806 MDD_DSAL “Destination Memory DMA Start Address
Registers (MDD_DSAH, MDD_DSAL)” on
page 9-35
0xFFC0 3808 MDD_DCT “Source Memory DMA Transfer Count Reg-
ister (MDD_DCT)” on page 9-40
Table B-13. SPI1 Controller Registers (Cont’d)
Memory- Mapped
Address Register Name See Section