Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-53
Memory
Latency
When cache is enabled, the bus between the core and L2 memory is fully
pipelined for contiguous burst transfers. The cache line fill from on-chip
memory behaves the same for instruction and data fetches. Operations
that miss the cache trigger a cache line replacement. This replacement fills
one 256-bit (32-byte) line with four 64-bit reads. Under this condition,
the L1 cache line fills from the L2 SRAM in
7+1+1+1=10
cycles. In other
words, after seven core cycles, the first 64-bit (8-byte) fill is available for
the processor.
Figure 6-19 shows an example of L2 latency with cache on.
Figure 6-18. L2 Memory Map
0xF000 0000
Memory Bank 0
(32 KByte)
Memory Bank 1
(32 KByte)
0xF002 0000
0xF002 8000
Memory Bank 2
(32 KByte)
Memory Bank 3
(32 KByte)
0xF000 8000
0xF001 0000
0xF001 8000
0xF003 FFFF
0xF003 0000
0xF003 8000
Memory Bank 4
(32 KByte)
Memory Bank 5
(32 KByte)
Memory Bank 6
(32 KByte)
Memory Bank 7
(32 KByte)