Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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System Reset and Power-up Configuration
3-12 ADSP-BF535 Blackfin Processor Hardware Reference
System Reset and Power-up
Configuration
Table 3-6 describes the five types of ADSP-BF535 processor resets. Note
all resets, except System Software, reset the core.
PLL Bypass mode Determined by sampling BYPASS pin at reset
Core clock/system clock ratio Determined by sampling SSEL pins at reset
Peripheral clocks Enabled
Table 3-6. ADSP-BF535 Processor Resets
Reset Source Result
Hardware reset The ADSP-BF535 processor
RESET
pin causes a hardware
reset.
Resets both the core and the peripherals,
including the Dynamic Power Manage-
ment Controller (DPMC).
Resets the No Boot on Software Reset bit
in
SYSCR
. For more information, see
“System Reset Configuration Register
(SYSCR)” on page 3-14
.
System Software
reset Writing b#111 to bits [2:0]
in the system MMR
SWRST
at address 0xFFC0 0410
causes a System Software
reset.
Resets only the peripherals, excluding the
RTC (Real-Time Clock) block and most
of the DPMC. The DPMC resets only
the Peripheral Clock Enable register
(
PLL_IOCK
) and the No Boot on Software
Reset bit in
SYSCR
. Does not reset the
core.
Table 3-5. Processor State on Reset (Cont’d)
Item Description of Reset State