Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference G-17
MAC (Multiply/Accumulate).
A floating-point operation that multiplies two numbers and then adds a
third to get the result. See
Multiply Accumulator .
memory bank.
A unit of the processor’s external memory space, which may be addressed
by either data address generator. External memory banks also may be con-
figured for size and access waitstates.
memory block.
A unit of the processor’s internal memory space, which is associated with a
DAG.
Memory Management Unit (MMU).
A component of the ADSP-BF535 processor that supports protection and
selective caching of memory by using CPLBs.
Mode Register.
SDRAM devices contain an internal configuration register which allows
specification of the SDRAM device’s functionality. After power-up and
before executing a read or write to the SDRAM memory space, the appli-
cation must trigger the SDC to write the SDRAM’s mode register. The
write of the SDRAM’s mode register is triggered by writing a 1 to the
PSSE
bit in the SDRAM Memory Global Control register (
EBIU_SDGCTL
) and
then issuing a read or write transfer to the SDRAM address space. The ini-
tial read or write triggers the SDRAM power-up sequence to be run,
which programs the SDRAM’s mode register with the CAS latency from
the
EBIU_SDGCTL
register. This initial read or write to SDRAM takes many
cycles to complete. Note that for most applications the SDRAM power-up
sequence and writing of the mode register needs to be done only once.
Once the power-up sequence has completed, the
PSSE
bit should not be
set again unless a change to the mode register is desired.