Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 8-19
Dynamic Power Management
• If the
PLL_CTL
register is programmed to enter the Sleep operating
mode, the processor immediately transitions to the Sleep mode and
waits for a wake-up signal before continuing. When the wake-up
signal has been asserted, the instruction sequence continues with
the
STI
instruction, as described in the section, “PLL Programming
Sequence Continues” on page 8-19 causing the processor to transi-
tion to:
• – Active mode if
BYPASS
in the
PLL_CTL
register is set
• – Full On mode if the
BYPASS
bit is cleared
• If the
PLL_CTL
register is programmed to enter the Deep Sleep
operating mode, the processor immediately transitions to the Deep
Sleep mode and waits for a Real-Time Clock (RTC) interrupt or
hardware reset signal:
• – An RTC interrupt causes the processor to enter the Active
operating mode and continue with the
STI
instruction in
the sequence, as described below.
• – A hardware reset causes the processor to execute the reset
sequence, as described in “Hardware Reset” on page 3-13 .
• If no operating mode transition is programmed, the processor waits
for a wake-up signal to continue with the
STI
instruction in the
sequence, as described in the section below.
PLL Programming Sequence Continues
The instruction sequence shown in Listing 8-1 on page 8-18 then contin-
ues with the
STI
instruction. Interrupts are re-enabled,
IMASK
is restored
and normal program flow resumes.

To prevent spurious activity, DMA should be suspended while exe-
cuting this instruction sequence.