Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 440 / 1022

SPI General Operation
10-34 ADSP-BF535 Blackfin Processor Hardware Reference
Slave Mode Operation
When a device is enabled as a slave (and DMA mode is not selected), the
start of a transfer is triggered by a transition of the
SPISS
select signal to
the active state (low) or by the first active edge of the clock (
SCK
), depend-
ing on the state of
CPHA
.
These steps illustrate SPI operation in the slave mode:
• The core writes to
SPIx_CTL
to define the mode of the serial link to
be the same as the mode setup in the SPI master.
• To prepare for the data transfer, the core writes data to be trans-
mitted into
SPIx_TDBR
.
• Once the
SPISS
falling edge is detected, the slave starts sending and
receiving data on active
SCK
edges.
• Reception/transmission continues until
SPISS
is released or until
the slave has received the proper number of clock cycles.
• The slave device continues to receive/transmit with each new fall-
ing edge transition on
SPISS
and/or active
SCK
clock edge.
10 Transmit or
Receive with
DMA Initiate new multiword trans-
fer upon write to DMA enable
bit. Individual word transfers
begin with either a DMA write
to SPIx_TDBR or a DMA read
of SPIx_RDBR (depending on
TRAN bit), and last transfer
complete Interrupt active upon DMA
error or multiword transfer
complete
Write 1 to SPIx_DMA_INT
register clears interrupt
11 Reserved N/A N/A
Table 10-19. Transfer Initiation (Cont’d)
TIMOD Function Transfer Initiated Upon Action, Interrupt