EBIU Programming Model
18-8
ADSP-BF535 Blackfin Processor Hardware Reference
There are 6 control registers and 1 status register in the EBIU. They are:
• Asynchronous Memory Global Control register (
EBIU_AMGCTL
)
• Asynchronous Memory Bank Control 0 register (
EBIU_AMBCTL0
)
• Asynchronous Memory Bank Control 1 register (
EBIU_AMBCTL1
)
• SDRAM Memory Global Control register (
EBIU_SDGCTL
)
• SDRAM Memory Bank Control register (
EBIU_SDBCTL
)
• SDRAM Refresh Rate Control register (
EBIU_SDRRC
)
• SDRAM Control Status register (
EBIU_SDSTAT
)
Each of these registers is described in detail in the AMC and SDC sections
later in this chapter.
In addition to the EBIU control and status registers (system MMRs)
described in this chapter, the clock distributed to the EBIU has a
dedicated enable, located in the
IOCK
register of the PLL control.
For more
information, see “Peripheral Clock Enable Register (PLL_IOCK)” on
page 8-22.
Error Detection
The EBIU responds to any operation which addresses the range of 0x0000
0000 - 0xDFFF FFFF, even if that bus operation addresses reserved or dis-
abled memory. It responds by completing the bus operation (asserting the
appropriate number of acknowledges as specified by the bus master) and
by asserting the EAB or EMB bus error signal for these error conditions:
• Any access to reserved memory space
• Any access to a disabled external memory bank
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...