Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Memory Architecture
6-38 ADSP-BF535 Blackfin Processor Hardware Reference
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Critical processor applications can take advantage of this memory
organization so that one data bank can be configured as data cache
to support other software functions.
L1 Data SRAM
Each of the 16 KB SRAM regions implemented for Data Bank A and Data
Bank B is further divided into four sub-banks. Like the organization of L1
Instruction Memory, this organization provides an effective dual port
capability that gives the system DMA simultaneous access to the
SRAMs—provided that collisions to the same sub-bank do not occur.
Each of these regions is single ported, and if address collision is detected,
access is granted first to system DMA, then to the DAGs.
The division of each data bank into four sub-banks allows code optimiza-
tion that permits two simultaneous, parallel DAG references to the same
data bank. The division into sub-banks and subsequent code optimization
also permit system DMA access—for example, to preload or postunload
data buffers. For more information, see
“Data Address Generators” on
page 5-1 .
Table 6-5. Data Memory Configure Bits
ENDM DMC[1:0] Configuration
0 xx Data Bank A is disabled; Data Bank B is disabled
1 00 Data Bank A is SRAM; Data Bank B is SRAM. This is the
default state at reset.
1 01 Reserved
1 10 Data Bank A is cache; Data Bank B is SRAM
1 11 Data Bank A is cache; Data Bank B is cache