Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 18-55
External Bus Interface Unit
To calculate the value that should be written to the
EBIU_SDRRC
register,
use this equation:
RDIV
= ((f
SCLK

t
REF
)/NRA) - (t
RAS
+ t
RP
)
Where:
• f
SCLK
=
SCLK
frequency (system clock frequency)
• t
REF
= SDRAM refresh period
• NRA = Number of row addresses in SDRAM (refresh cycles to
refresh whole SDRAM)
• t
RAS
= Active to Precharge time (
TRAS
in the SDRAM Memory
Global Control register) in number of clock cycles
• t
RP
= RAS to Precharge time (
TRP
in the SDRAM Memory Global
Control register) in number of clock cycles
This equation calculates the number of clock cycles between required
refreshes and subtracts the required delay between Bank Activate com-
mands to the same bank (t
RC
= t
RAS
+ t
RP
). The t
RC
value is subtracted, so
that in the case where a refresh time-out occurs while an SDRAM cycle is
active, the SDRAM refresh rate specification is guaranteed to be met. The
result from the equation should always be rounded down to an integer.
Figure 18-17. SDRAM Refresh Rate Control Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 1
SDRAM Refresh Rate Control Register (EBIU_SDRRC)
RDIV
Reset = 0x081A
0xFFC0 4C0A