Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Addressing With DAGs
5-4 ADSP-BF535 Blackfin Processor Hardware Reference
Addressing With DAGs
The DAGs can generate an address that is incremented by a value or by a
register. In post-modify addressing, the DAG outputs the I-register value
unchanged; then the DAG adds an M-register or immediate value to the
I-register.
In Indexed addressing, the DAG adds a small offset to the value in the
P-register, but does not update the P-register with this new value, thus
providing an offset for that particular memory access.
The ADSP-BF535 processor addressing is always byte aligned. Depending
on the type of data used, increments and decrements to the DAG registers
can be by 1, 2, or 4 to match the 8-bit, 16-bit, or 32-bit accesses.
For example, consider this instruction:
R0 = [ P3++ ]
;
This instruction fetches a 32-bit word, pointed to by the value in
P3
, and
places it in
R0
. It then post-increments
P3
by four , maintaining alignment
with the 32-bit access.
R0.L = W [ I3++ ] ;
This instruction fetches a 16-bit word, pointed to by the value in
I3
and
places it in the low half of the destination register,
R0.L
. It then
post-increments
I3
by two , maintaining alignment with the 16-bit access.
R0 = B [ P3++ ] (X) ;
This instruction fetches an 8-bit word, pointed to by the value in
P3
and
places it in the destination register,
R0
. It then post-increments
P3
by one ,
maintaining alignment with the 8-bit access. The byte value may be
zero-extended or sign-extended into the 32-bit data register.
Instructions using Index registers use an M-register or a small immediate
value (+/– 2 or 4) as the modifier. Instructions using Pointer registers use
a small immediate value or another P-register as the modifier. For instruc-
tion summary details, see
Table 5-3 on page 5-17 .