Memory Protection and Properties
6-60
ADSP-BF535 Blackfin Processor Hardware Reference
• Valid
Check this bit to determine whether this is valid CPLB data.
• Lock
Keep this entry in MMR; do not participate in CPLB replacement
policy.
Page Descriptor Table
For memory accesses to utilize the cache when CPLBs are enabled for
instruction access, data access, or both, a valid CPLB entry must be avail-
able in an MMR pair. The MMR storage locations for CPLB entries are
limited to 16 descriptors for instruction fetches and 16 descriptors for
data load and store operations.
For small and/or simple memory models, it may be possible to define a set
of CPLB descriptors that fit into these 32 entries, cover the entire address-
able space, and never need to be replaced. This type of definition is
referred to as a
static
memory management model.
However, operating environments commonly define more CPLB descrip-
tors to cover the addressable memory and I/O spaces than will fit into the
available on-chip CPLB MMRs. When this happens, a memory-based
data structure, called a Page Descriptor Table, is used; in it can be stored
all the potentially required CPLB descriptors. As in many RISC architec-
tures, the specific format for the Page Descriptor Table is not defined as
part of the Blackfin processor architecture. Different operating systems,
which have different memory management models, can implement Page
Descriptor Table structures that are consistent with the OS requirements.
This allows adjustments to be made between the level of protection
afforded versus the performance attributes of the memory-management
support routines.
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...