Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-45
Memory
Data Cache Access
The cache controller tests the address from either DAG against the tag
bits. If the logical address is present in L1 cache, a cache hit occurs, and
the data is accessed in L1. If the logical address is not present, a cache miss
occurs, and the memory transaction is passed to the next level of memory
via the system interface. The line index and replacement policy for the
cache controller determines the cache tag and data space that are allocated
for the data coming back from L2 memory via the System Bus Interface
Unit (SBIU).
A data cache line is in one of three states: invalid, exclusive (valid and
clean), and modified (valid and dirty). If valid data already occupies the
allocated line space and the cache is configured for write-back storage, the
controller checks the state of the cache line and treats it accordingly:
• If the state of the line is exclusive (clean), the new tag and data
write over the old line.
• If the state of the line is modified (dirty), then the cache contains
the only valid copy of the data.
• If the line is dirty, the current contents of the cache are copied back
to L2 memory before the new data is written to the cache.
The ADSP-BF535 processor provides victim buffers and line fill buffers.
These buffers are used if a cache load miss generates a victim cache line
that should be replaced. The line fill operation goes to the L2 memory via
the SBIU before the victim copyback operation. The data cache performs
the line fill request to the system as critical, or requested, word first and
forwards that data to the waiting DAG as it updates the cache line. In
other words, the cache performs critical word forwarding.