Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 1-23
Introduction
sor is effectively shut down while all peripherals continue to operate.
Without clocking to the processor core, significant power savings are
achieved.
Deep Sleep Operating Mode (Maximum Power
Savings)
The Deep Sleep mode maximizes power savings by disabling the clocks to
the processor core and to all synchronous systems. Asynchronous systems,
such as the RTC, continue to operate but access to processor resources is
limited. This powered-down mode can only be exited by assertion of the
reset interrupt or by an interrupt generated by the RTC.
Clock Signals
The ADSP-BF535 processor can be clocked by a sine wave input or a buff-
ered, shaped clock derived from an external clock oscillator.
The processor provides a user-programmable 1 to 31 multiplication of the
input clock to support external to internal (processor core) clock ratios. At
runtime, the multiplication factor can be controlled in software.
All on-chip peripherals operate at the rate set by the system clock. The sys-
tem clock frequency is programmable by the PLL Control register. The
programmable values define a divide ratio between the core clock (CCLK)
and the system clock (SCLK).