Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-9
Serial Port Controllers
Transmit and Receive Configuration Registers
(SPORTx_TX_CONFIG, SPORTx_RX_CONFIG)
The main control registers for each SPORT are the transmit configuration
register,
SPORTx_TX_CONFIG
, shown in Figure 11-3 on page 11-10 , and the
receive configuration register,
SPORTx_RX_CONFIG
, shown in Figure 11-4
on page 11-14 .
A SPORT is enabled for transmit if Bit 0 (
TSPEN
) of the Transmit Config-
uration register is set to 1; it is enabled to receive if Bit 0 (
RSPEN
) of the
Receive Configuration register is set to 1. Both of these bits are cleared
during either a hard reset or a soft reset, disabling all SPORT channels.
When the SPORT is enabled to transmit (
TSPEN
set) or receive (
RSPEN
set),
corresponding SPORT configuration register writes are disabled except
for
SPORTx_RSCLKDIV
,
SPORTx_TSCLKDIV
, and multichannel mode channel
enable registers. Writes are always enabled to the
SPORTx_TX
buffer.
SPORTx_RX
is a read-only register.
After a write to a SPORT register, any changes to the control and mode
bits generally take effect when the SPORT is re-enabled.
When changing operating modes, a SPORT control register should be
cleared before the new mode is written to the register.
The
TXS
status bit in the SPORT Status register indicates whether the
SPORTx_TX
buffer is full (
1
) or empty (
0
).
The Transmit Underflow Status bit (
TUVF
) in the SPORT Status register is
set whenever the
TFS
signal occurs from either an external or an internal
source while the
SPORTx_TX
buffer is empty. The internally generated
TFS
may be suppressed whenever
SPORTx_TX
is empty by clearing the
DITFS
control bit in the SPORT Configuration register.
When
DITFS
=
0
(the default), the internal transmit frame sync signal (
TFS
)
is dependent upon new data being present in the
SPORTx_TX
buffer; the
TFS
signal is only generated for new data. Setting
DITFS
to 1 selects data