Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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L1 Instruction Memory Controller Registers
A-4 ADSP-BF535 Blackfin Processor Hardware Reference
L1 Instruction Memory Controller
Registers
Table A-2 lists the MMR assignments for the L1 Instruction Memory
Controller registers (0xFFE0 1004–0xFFE0 6100).
0xFFE0 023C DCPLB_DATA15 “DCPLB Data Registers (DCPLB_DATAx)”
on page 6-65
0xFFE0 0300 DTEST_COMMAND “Data Test Command Register
(DTEST_COMMAND)” on page 6-49
0xFFE0 0400 DTEST_DATA0 “Data Test Data 0 Register
(DTEST_DATA0)” on page 6-50
0xFFE0 0404 DTEST_DATA1 “Data Test Data 1 Register
(DTEST_DATA1)” on page 6-49
0xFFE0 0408 DTEST_DATA2 “Data Test Data 0 Register
(DTEST_DATA0)” on page 6-50
0xFFE0 040C DTEST_DATA3 “Data Test Data 1 Register
(DTEST_DATA1)” on page 6-49
Table A-2. L1 Instruction Memory Controller Registers
Memory- Mapped
Address Register Name See Section
0xFFE0 1004 IMEM_CONTROL “Instruction Memory Control Register
(IMEM_CONTROL)” on page 6-12
0xFFE0 1008 ICPLB_STATUS “ICPLB Status Register (ICPLB_STATUS)”
on page 6-74
0xFFE0 100C ICPLB_FAULT_ADDR “ICPLB Fault Address Register
(ICPLB_FAULT_ADDR)” on page 6-76
Table A-1. L1 Data Memory Controller Registers (Cont’d)
Memory- Mapped
Address Register Name See Section