Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 12-37
UART Port Controller
IrDA Transmitter Description
To generate the IrDA pulse transmitted by the UART, the normal NRZ
output of the transmitter is first inverted, so a 0 is transmitted as a high
pulse of 16 UART clock periods and a 1 is transmitted as a low pulse for
16 UART clock periods. The leading edge of the pulse is then delayed by
six UART clock periods. Similarly, the trailing edge of the pulse is trun-
cated by eight UART clock periods. This results in the final representation
of the original 0 as a high pulse of only 3/16 clock periods in a 16-cycle
UART clock period. The pulse is centered around the middle of the bit
time, as shown in
Figure 12-29 . The final IrDA pulse is fed to the off-chip
infrared driver.
This modulation approach ensures a pulse width output from the UART
of three cycles high out of every 16 UART clock cycles. As shown in
Table 12-9 on page 12-12 , the error terms associated with the baud rate
generator are very small and well within the tolerance of most infrared
transceiver specifications.
Figure 12-29. IrDA Transmit Pulse
0
1 0
8/16
9/16 7/16
16/16
NRZ
Inverted
Final
IrDA
8/16
9/16 7/16
16/16