Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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Interrupts With and Without Nesting
4-52 ADSP-BF535 Blackfin Processor Hardware Reference
/* Execute RTI, which jumps to return address, re-enables inter-
rupts, and switches to User mode if this is the last nested
interrupt in service. */
RTI;
The
RTI
instruction causes the return from an interrupt. The return
address is popped into the
RETI
register from the stack, an action that sus-
pends interrupts from the time that
RETI
is restored until
RTI
finishes
executing. The suspension of interrupts prevents a subsequent interrupt
from corrupting the
RETI
register.
Next, the
RTI
instruction clears the highest priority bit that is currently set
in
IPEND
. The processor then jumps to the address pointed to by the value
in the
RETI
register and re-enables the interrupts by clearing
IPEND[4]
.
Logging of Nested Interrupt Requests
The SIC detects level-sensitive interrupt requests from the peripherals.
The CEC provides edge-sensitive detection for its general-purpose inter-
rupts (
IVG7-IVG15
). Consequently, the SIC generates a synchronous
interrupt pulse to the CEC and then waits for interrupt acknowledgement
from the CEC. When the interrupt has been acknowledged by the core
(via assertion of the appropriate
IPEND
output), the SIC generates another
synchronous interrupt pulse to the CEC if the peripheral interrupt is still
asserted. This way, the system does not lose peripheral interrupt requests
that occur during servicing of another interrupt.
Because multiple interrupt sources can map to a single core processor gen-
eral-purpose interrupt, multiple pulse assertions from the SIC can occur
simultaneously, before, or during interrupt processing for an interrupt
event that is already detected on this interrupt input. For a shared inter-
rupt, the
IPEND
interrupt acknowledge mechanism described above
re-enables all shared interrupts. If any of the shared interrupt sources are