Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 8-3
Dynamic Power Management
PLL Clock Multiplier Ratios
The PLL Control register (
PLL_CTL
) governs the operation of the PLL. For
details about the
PLL_CTL
register, see “PLL Control Register (PLL_CTL)”
on page 8-7 .
The Divide Frequency (
DF
) bit and Multiplier Select (
MSEL[6:0]
) field
configure the various PLL clock dividers:
• The
DF
bit enables the input divider
• The
MSEL[6]
bit enables the output divider
• The
MSEL[5:0]
bits control the feedback dividers
• The feedback divider is composed in two stages, a divide by N
(1:32), selected by
MSEL[4:0],
and a divide by 2, selected by
MSEL[5]
.
Figure 8-1. PLL Conceptual Block Diagram
P
H
A
S
E
D
E
T
E
C
T
/1
/2
OR
/1
/2
OR
L
O
O
P
F
IL
T
E
R
VCO
CLKIN
DF
MSEL[6:0]
SSEL[1:0]
/N
CCLK
SCLK
/M
/2
MSEL [5] MSEL[4:0]
MSEL[6]
ENABLE /
DISABLE
/1
/2
OR
PDWN
STOPCK
BYPASS