Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-54 ADSP-BF535 Blackfin Processor Hardware Reference
SDRAM Refresh Rate Control Register (EBIU_SDRRC)
The SDRAM Refresh Rate Control register, shown in Figure 18-17 , pro-
vides a flexible mechanism for specifying the Auto-Refresh timing. The
SDC provides a programmable refresh counter which has a period based
on the value programmed into the
RDIV
field of this register, that coordi-
nates the supplied clock rate with the SDRAM device’s required refresh
rate.
The delay (in number of
SCLK
cycles) desired between consecutive refresh
counter time-outs must be written to the
RDIV
field. A refresh counter
time-out triggers an Auto-Refresh command to all external SDRAM
banks. Write the
RDIV
value to the
EBIU_SDRRC
register before the SDRAM
power-up sequence is triggered. Change this value only when the SDC is
idle.
Figure 18-16. SDRAM Control Status Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0
SDRAM Control Status Register (EBIU_SDSTAT)
SDSRA
SDPUA
SDCI
SDRS
SDEASE - W1C
SDEMSE - W1C
SDRAM EMB sticky error status
0 - No error detected
1 - EMB access generated an error
SDRAM EAB sticky error status
0 - No error detected
1 - EAB access generated an error
SDRAMs in reset state
0 - A power-up sequence has been
initiated since the last SDC reset
1 - A power-up sequence has not
occurred since an SDC reset
occurred
SDRAM controller idle
0 - SDC is busy performing
an access or an auto
refresh
1 - SDC is idle
SDRAM self-refresh active
0 - SDRAMs not in self-
refresh mode
1 - SDRAMs in self-refresh
mode
SDRAM power-up active
0 - SDC not in power-up
sequence
1 - SDC in power-up
sequence
Reset = 0x0008
0xFFC0 4C0E