ADSP-BF535 Blackfin Processor Hardware Reference
18-85
External Bus Interface Unit
When the external buffer timing (
EBUFE = 1
in the SDRAM Memory
Global Control register) and/or CAS latency of 3 (
CL = 11
in the SDRAM
Memory Global Control register) is used, all accesses take one extra cycle
for each feature selected. Accesses that hit in the Read Buffer follow these
rules:
If either
EBUFE = 1
or
CL = 11
:
• For N = 16 to 13, N half word hit: 8 words/8 cycles
• For N = 12 to 0, N half word hit: 8 words/(22 – N) cycles
If both
EBUFE = 1
and
CL = 11
:
• For N = 16 to 14, N half word hit: 8 words/8 cycles
• For N = 13 to 0, N half word hit: 8 words/(23 – N) cycles
Summary of Contents for ADSP-BF535 Blackfin
Page 80: ...Development Tools 1 26 ADSP BF535 Blackfin Processor Hardware Reference...
Page 312: ...Working With Memory 6 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 332: ...System Interfaces 7 20 ADSP BF535 Blackfin Processor Hardware Reference...
Page 360: ...Dynamic Power Management Controller 8 28 ADSP BF535 Blackfin Processor Hardware Reference...
Page 446: ...Beginning and Ending an SPI Transfer 10 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 522: ...Timing Examples 11 76 ADSP BF535 Blackfin Processor Hardware Reference...
Page 562: ...IrDA Support 12 40 ADSP BF535 Blackfin Processor Hardware Reference...
Page 608: ...PCI I O Issues 13 46 ADSP BF535 Blackfin Processor Hardware Reference...
Page 672: ...References 14 64 ADSP BF535 Blackfin Processor Hardware Reference...
Page 810: ...SDRAM Controller SDC 18 86 ADSP BF535 Blackfin Processor Hardware Reference...
Page 811: ...ADSP BF535 Blackfin Processor Hardware Reference 18 87 External Bus Interface Unit...
Page 812: ...SDRAM Controller SDC 18 88 ADSP BF535 Blackfin Processor Hardware Reference...
Page 860: ...DMA Bus Debug Registers 20 30 ADSP BF535 Blackfin Processor Hardware Reference...