Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-56 ADSP-BF535 Blackfin Processor Hardware Reference
Below is an example of the calculation of
RDIV
for a typical SDRAM in a
system with a 133 MHz clock:
• f
SCLK
= 133 MHz
• t
REF
= 64 ms
• NRA = 4096 row addresses
• t
RAS
= 2
• t
RP
= 2
The equation for
RDIV
yields:
RDIV
= ( (133

10
6

64

10
-3
) / 4096) – (2 + 2) = 2074 clock cycles.
This means
RDIV
is 0x81A (hex) and the SDRAM Refresh Rate Control
register should be written with 0x081A.
Note that
RDIV
must be programmed to a nonzero value if the SDRAM
controller is enabled. When
RDIV = 0
, operation of the SDRAM controller
is not supported and can produce undesirable behavior. Values for
RDIV
can range from 0x001 to 0xFFF.
SDRAM External Bank Address Decode
The memory address space for each SDRAM bank is contiguous. There-
fore, the starting addresses for each of the SDRAM banks and for the
beginning of the unpopulated/reserved space is determined by adding up
the sizes of each bank that precedes that bank. This can be done by simply
summing the Bank Size Encodings listed in
Table 18-6 for each bank as
shown in Table 18-7 . If every SDRAM bank is 128 MB, the SDRAM
address space is fully populated. If any bank is less than 128 MB, the
address space after bank3 is referred to as “unpopulated/reserved” space.