Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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UARTx Control and Status Registers
12-6 ADSP-BF535 Blackfin Processor Hardware Reference
UARTx Receive Buffer Registers (UARTx_RBR)
The receive operation uses the same data format as the transmit configura-
tion, except that the number of stop bits is always 1. After detection of the
start bit, the received word is shifted into the Receive Shift register (
RSR
)
at a bit rate of
SCLK/(16

Divisor)
. After the appropriate number of bits
(including stop bits) is received, the data and any status are updated and
the Receive Shift register is transferred to the UARTx Receive Buffer reg-
ister (
UARTx_RBR
), shown in Figure 12-5 . After the transfer of the received
word to the
UARTx_RBR
buffer and the appropriate synchronization delay,
the Data Ready (
DR
) status flag is updated.
A sampling clock equal to 16 times the baud rate samples the data as close
to the midpoint of the bit as possible. Because the internal sample clock
may not exactly match the asynchronous receive data rate, the sampling
point drifts from the center of each bit. The sampling point is resynchro-
nized with each start bit, so the error accumulates only over the length of a
single word. A receive filter removes spurious pulses of less than two times
the sampling clock period.
The
UARTx_RBR
register is mapped to the same address as
UARTx_THR
and
UARTx_DLL
. To access
UARTx_RBR
, the
DLAB
bit in
UARTx_LCR
must be
cleared. When the
DLAB
bit is cleared, writes to this address target the
UARTx_THR
register, while reads from this address return the
UARTx_RBR
register.
Table 12-3. UARTx Transmit Holding Register MMR Assignments
Register Name Memory-Mapped Address
UART0_THR 0xFFC0 1800
UART1_THR 0xFFC0 1C00