Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-17
Serial Port Controllers
and externally generated frame syncs are sampled on the rising
edge. If cleared, internally generated frame syncs are driven on the
rising edge, and data and externally generated frame syncs are sam-
pled on the falling edge.
SPORTx Transmit (SPORTx_TX) Registers
The
SPORTx_TX
register, shown in Figure 11-5 , acts as the transmit data
buffer for the SPORT. It is a 16-bit register which must be loaded with
the data to be transmitted; the data is loaded either by the DMA control-
ler or by the program running on the core. Word lengths of less than 16
bits are right justified.
The SPORT transmit registers act like a two-location FIFO because there
is a data register (
SPORTx_TX
) with an accompanying output shift register
as shown in Figure 11-1 on page 11-5 . Two 16-bit words may be stored in
these registers at any one time. When the
SPORTx_TX
register is loaded and
any previous word has been transmitted, the contents are automatically
loaded into the output shifter. An interrupt is generated when the output
shifter has been loaded, signifying that the
SPORTx_TX
register is ready to
accept the next word (the
SPORTx_TX
buffer is “not full”). This interrupt
does not occur if SPORT DMA is enabled.
The transmit underflow status bit (
TUVF
) is set in the SPORT Status regis-
ter when a transmit frame sync occurs and no new data has been loaded
into the serial shift register. In multichannel mode,
TUVF
is set whenever
the serial shift register is not loaded, when that transmission should begin
on an enabled channel. The
TUVF
status bit is cleared on a hard reset. From
that moment on, if it is set, it stays set until the SPORT is re-enabled (dis-
abled and then enabled again). Once the SPORT is enabled, it takes at
least 4 transmit clock cycles to clear the
TUVF
bit.