Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-46 ADSP-BF535 Blackfin Processor Hardware Reference
Selecting the CAS Latency Value (CL)
The CAS latency value defines the delay, in number of
SCLK
cycles,
between the time the SDRAM detects the Read command and the time it
provides the data at its output pins.
CAS latency does not apply to write cycles.
The
CL
bits in the SDRAM Memory Global Control register
(
EBIU_SDGCTL
) select the CAS latency value:
CL = 00
Reserved
CL = 01
Reserved
CL = 10
2 clock cycles
CL = 11
3 clock cycles
Generally, the frequency of operation determines the value of the CAS
latency. For specific information about setting this value, consult the
SDRAM device documentation.