Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 3-11
Operating Modes and States
The processor remains in the Reset state as long as external logic asserts
the external
RESET
signal. Upon deassertion, the processor completes the
reset sequence and switches to Supervisor mode, where it executes code
found at the reset event vector identified in the Event Vector Table
(EVT).
Software in Supervisor or Emulation mode can invoke the Reset state
without involving the external
RESET
signal by issuing the Reset version of
the
RAISE
instruction. After the reset sequence, the processor returns to
the Supervisor or Emulation mode that issued the
RAISE
instruction.
Application programs in User mode cannot invoke the Reset state, except
through a system call provided by an operating system kernel.
Table 3-5
summarizes the state of the processor upon reset.
Table 3-5. Processor State on Reset
Item Description of Reset State
Core
Operating mode Supervisor mode in reset event
Rounding mode Unbiased rounding
Cycle counters Disabled
DAG registers (I,L,B,M) Random values (must be cleared at initialization)
Data and address registers Random values (must be cleared at initialization)
IPEND, IMASK, ILAT Cleared, interrupts globally disabled with IPEND bit 4
CPLBs Disabled
L1 instruction memory SRAM (cache disabled)
L1 data memory SRAM (cache disabled)
Cache validity bits Random (must be set to invalid prior to cache initialization)
System
Booting methods Determined by the values of BMODE pins at reset
MSEL clock frequency Determined by sampling MSEL pins at reset