Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 11-23
Serial Port Controllers
SPORTx Status (SPORTx_STAT) Registers
The
RXS
and
TXS
status bits in the SPORT Status register are updated
upon reads and writes from the core processor even when the serial port is
disabled. The SPORT Status register is used to determine if the access to a
SPORT
RX
or
TX
buffer can be made by determining their full or empty
status. It is a read-only register. The reset value is undefined. The
SPORTx Status register is shown in
Figure 11-11 .
The transmit underflow status bit (
TUVF
) is set in the SPORT Status regis-
ter when a transmit frame sync occurs and no new data has been loaded
into the
SPORTx_TX
register. The
TUVF
status bit is sticky and is only
cleared by disabling the serial port.
Figure 11-10. SPORTx Receive Frame Sync Divider Register
Table 11-9. SPORTx Receive Frame Sync Divider Register MMR
Assignments
Register Name Memory-Mapped Address
SPORT0_RFSDIV 0xFFC0 280E
SPORT1_RFSDIV 0xFFC0 2C0E
SPORTx Receive Frame Sync Divider Register (SPORTx_RFSDIV)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Frame Sync Divider[15:0]
Reset = 0x0000
Number of receive clock
cycles counted before gener-
ating RFS pulse
For MMR
assignments, see
Table 11-9 .