Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 6-21
Memory
Line Fill Buffer
As the new cache line is retrieved from L2 memory, each 64-bit word is
buffered in a four-entry line fill buffer before it is written to a 4 KB mem-
ory bank within L1 memory. The line fill buffer allows the core to access
the data from the new cache line as the line is being retrieved from exter-
nal memory, rather than having to wait until the line has been written into
the cache.
The line fill buffer organization is shown in Figure 6-8 .
During a line fill operation, the line fill buffer’s address tag contains the
upper 18 bits plus bits 11 and 10 of the instruction fetch address. The
contents of the Way field identify the cache Way selected for replacement
(see
Table 6-3 ). Both fields are loaded at the end of a tag-address compare
operation that results in a cache miss.
Table 6-2. Cache Line Word Fetching Order
Target Word Fetching Order for Next Three Words
WD0 WD0, WD1, WD2, WD3
WD1 WD1, WD2, WD3, WD0
WD2 WD2, WD3, WD0, WD1
WD3 WD3, WD0, WD1, WD2
Figure 6-8. Line Fill Buffer Organization
ADDRESS TAG WAY WORD 0 V WORD 1 V WORD 2 V WORD 3 V
VALID BITS