Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 15-3
Programmable Flags
Reading either the Flag Set or Flag Clear registers returns the value of the
PFx
pins. The value returned shows the state of the
PFx
pins defined as
outputs and the sense of
PFx
pins defined as inputs, based on the polarity
and sensitivity settings of each pin.
The Flag Set register is a write-1-to-set register, while the Flag Clear regis-
ter is a write-1-to-clear register. These registers are used to set or clear the
output state associated with each output
PFx
pin, and to set or clear the
latched interrupt state captured from each input
PFx
pin. This mechanism
allows for more straightforward coding and is less prone to bit manipula-
tion errors than traditional read-modify-write mechanisms.
As an example, assume
PF[0]
is configured as an output. Writing 0x0001
to the Flag Set register drives a logic 1 on the
PF[0]
pin without affecting
the state of any other
PFx
pins. Writing 0x0001 to the Flag Clear register
drives a logic 0 on the
PF[0]
pin without affecting the state of any other
PFx
pins. Reading either register shows 0s for those
PFx
pins defined as
outputs and driven low, 1s for those pins (including
PF[0]
) defined as out-
puts and driven high, and the present sense of those
PFx
pins defined as
inputs. Input sense is based on
FIO_POLAR
and
FIO_EDGE
settings, as well as
the logic level at each pin.
Figure 15-1. Flag Direction Register
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Flag Direction Register (FIO_DIR)
PF0 Direction
PF12 Direction
PF13 Direction
PF14 Direction
PF15 Direction
PF1 Direction
PF2 Direction
PF3 Direction
PF4 Direction
PF5 Direction
For all bits, 0 - Input, 1 - Output.
PF6 Direction
PF7 Direction
PF11 Direction
PF10 Direction
PF9 Direction
PF8 Direction
Reset = 0x0000
0xFFC0 2400