Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-60 ADSP-BF535 Blackfin Processor Hardware Reference
The following sections have tables which describe the muxing of the Inter-
nal Address (from the EAB or EMB buses) into the Row Address, Bank
Address, and Column Address, for all the combinations of SDRAM bank
width, and number of column address pins on the SDRAMs, and whether
the SDRAM is 16- or 32-bits wide. This muxing assumes the SDRAMs
have 4 internal banks.
All the possible configurations of SDRAM sizes and number of chips con-
nected in parallel are given for each muxing table.
Note there is no separate
ADDR[1]
pin on the ADSP-BF535 processor. The
ADDR[1]
pin is muxed onto the pin
ABE[3]
/
SDQM[3]
/
ADDR[1]
for 16-bit
SDRAM banks. This is further described in “Data Mask (SDQM[3:0])
Encodings” on page 18-67 .
32-Bit Wide SDRAM Address Muxing
Table 18-9 , Table 18-10 , Table 18-11 , and Table 18-12 show address
muxing for 32-bit wide SDRAM banks using SDRAMs with 8, 9, 10, or
11 column address pins.
Figure 18-19. Multiplexed SDRAM Addressing Scheme
Row
Address
31
25 0
Internal 32-bit Address
Bank
Select Column
Address Byte
Mask