Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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On-Chip Level 2 (L2) Memory
6-54 ADSP-BF535 Blackfin Processor Hardware Reference
In this example, at the end of ten core cycles, 32 bytes of instructions or
data have been brought into cache and are available to the sequencer. If all
the instructions contain 16 bits, sixteen instructions are brought into
cache at the end of ten cycles. In addition, the first instruction that is part
of the cache-line fill executes on the eighth cycle; the second instruction
executes on the ninth cycle, and the third instruction executes on the
tenth cycle—all of them in parallel with the cache line fill.
Each cache line fill is aligned on a 32-byte boundary. When the requested
instruction or data is not 32-byte aligned, the requested item is always
loaded in the first read; each read is forwarded to the core as the line is
filled. Sequential memory accesses miss the cache only when they reach
the end of a cache line.
When on-chip L2 memory is configured as non-cacheable, instruction
fetches and data fetches occur in 64-bit fills. In this case, each fill takes
seven core cycles to complete. As shown in
Figure 6-20 , on-chip L2
Figure 6-19. L2 Latency With Cache On
64 BITS
64 BITS
E F G H
I J
K L
M
N O P
A B C D
A B C
D
E F G H A B C D
INSTRUCTION ALIGNMENT UNIT
T+7 ABCD READY
TO EXECUTE
T+8 EFGH READY
TO EXECUTE
T+9 IJKL READY
TO EXECUTE
T+10 MNOP READY
TO EXECUTE
T+8 A EXECUTES
T+9 B EXECUTES
T+10 C EXECUTES
T+11 D EXECUTES
L2 MEMORY
T+13 F EXECUTES
T+12 E EXECUTES
E F G H
I
J K L
INSTRUCTION ALIGNMENT UNIT
NOTE: AFTER F EXECUTES, GHIJKLMNOP
EXECUTE ON CONSECUTIVE CYCLES.
AFTER P IS IN PIPELINE,
NEW CACHE LINE FILL IS INITIATED.
CYCLES
64 BITS 64 BITS 64 BITS
T+7 T+8 T+10 T+9
EACH INSTRUCTION FETCH IS 32 BYTES
INSTRUCTION ALIGNMENT UNIT