Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 12-17
UART Port Controller
DMA Mode
In this mode, separate receive (RX) and transmit (TX) DMA channels
move data between the UART and memory. The processor does not have
to move data, it just has to set up the appropriate transfers either through
the descriptor mechanism or through autobuffer mode.
No additional buffering is provided in the UART DMA channels, so the
latency requirements are the same as in non-DMA mode. However, the
latency is determined by the bus activity and arbitration mechanism and
not by the processor loading and interrupt priorities. For more informa-
tion, see
“Direct Memory Access” on page 9-1 .
The DMA interrupt mechanism works independently from the
UARTx_IER
and the
UARTx_IIR
registers. The TX DMA has its own dedicated inter-
rupt channel. The receive interrupt channel handles RX DMAs as well as
receive error conditions when enabled in the UARTx Receive DMA Con-
figuration register (
UARTx_CONFIG_RX
). DMA interrupt routines must
explicitly write ones to the corresponding DMA IRQ status registers
explicitly to clear the latched request of the pending interrupt.
Mixing Modes
Non-DMA and DMA modes use different synchronization mechanisms.
Consequently, any serial communication must be complete before switch-
ing from non-DMA to DMA mode or vice-versa. In other words, before
switching from non-DMA transmission to DMA transmission, make sure
that both
UARTx_THR
and the internal Transmit Shift register (
TSR
) are
empty by testing the
THRE
and the
TEMT
status bits in
UARTx_LSR
. Other-
wise, the processor must wait until the 2-bit DMA Buffer Status field
within the appropriate UARTx Transmit DMA Configuration register
(
UARTx_CONFIG_TX
) is clear.