Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

Page: 766 / 1022

SDRAM Controller (SDC)
18-42 ADSP-BF535 Blackfin Processor Hardware Reference
does a Precharge All command, followed by eight Auto-Refresh cycles,
and then a Load Mode Register command. Two events must occur before
the SDC does the SDRAM power-up sequence:
• The
PSSE
bit must be set to 1 to enable the SDRAM power-up
sequence.
• A read or write access must be done to enabled SDRAM address
space in order to have the external bus granted to the SDC so that
the SDRAM power-up sequence may occur. The SDRAM
power-up sequence is performed for all four SDRAM banks.
The SDRAM power-up sequence occurs and is followed immediately by
the read or write transfer to SDRAM that was used to trigger the SDRAM
power-up sequence. Note that there is a long latency for this first access to
SDRAM because the SDRAM power-up sequence takes many cycles to
complete.

Before executing the SDC power-up sequence, ensure that the
SDRAM receives stable power and is clocked for the proper
amount of time, as specified by the SDRAM specification.
When the
SRFS
bit is set to 1, Self-Refresh mode is triggered. Once the
SDC completes any active transfers, the SDC executes the sequence of
commands to put the SDRAM into Self-Refresh mode. The next access to
an enabled SDRAM bank causes the SDC to execute the commands to
exit the SDRAM from Self-Refresh and execute the access. See
“Entering
and Exiting Self-Refresh Mode (SRFS)” on page 18-44 for more informa-
tion about the
SRFS
bit.
The
EBUFE
bit is used to enable or disable external buffer timing. When
buffered SDRAM modules or discrete register-buffers are used to drive the
SDRAM control inputs,
EBUFE
should be set to 1. Using this setting adds a
cycle of data buffering to read and write accesses. See “Setting the
SDRAM Buffering Timing Option (EBUFE)” on page 18-45 for more
information about the
EBUFE
bit.