Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference B-11
System MMR Assignments
Timer Registers
Table B-8 lists the MMR assignments for the Timer registers
(0xFFC0 2000–0xFFC0 23FF).
0xFFC0 1F0C UART1_DESCR_RDY_TX “UARTx Transmit DMA Descriptor
Ready Registers
(UARTx_DESCR_RDY_TX)” on
page 12-34
0xFFC0 1F0E UART1_IRQSTAT_TX “UARTx Transmit DMA IRQ Status
Registers (UARTx_IRQSTAT_TX)”
on page 12-35
Table B-8. Timer Registers
Memory-Mapped
Address Register Name See Section
0xFFC0 2000 TIMER0_STATUS “Timer Status Registers
(TIMERx_STATUS)” on page 16-4
0xFFC0 2002 TIMER0_CONFIG “Timer Configuration Registers
(TIMERx_CONFIG)” on page 16-7
0xFFC0 2004 TIMER0_COUNTER_LO “Timer Counter Registers
(TIMERx_COUNTER)” on page 16-11
0xFFC0 2006 TIMER0_COUNTER_HI “Timer Counter Registers
(TIMERx_COUNTER)” on page 16-11
0xFFC0 2008 TIMER0_PERIOD_LO “Timer Period Registers
(TIMERx_PERIOD)” on page 16-10
0xFFC0 200A TIMER0_PERIOD_HI “Timer Period Registers
(TIMERx_PERIOD)” on page 16-10
0xFFC0 200C TIMER0_WIDTH_LO “Timer Width Registers
(TIMERx_WIDTH)” on page 16-11
Table B-7. UART1 Controller Registers (Cont’d)
Memory-Mapped
Address Register Name See Section