Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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SDRAM Controller (SDC)
18-34 ADSP-BF535 Blackfin Processor Hardware Reference
Many DIMMs also include a serial presence detect port, which provides
access to an on-DIMM serial ROM which includes information describ-
ing the type and characteristics of SDRAMs on the DIMM. This
information can be read to determine the type, size, and timing parame-
ters of installed DIMMs at boot time. One of the SPI or SPORT
peripherals of the ADSP-BF535 processor can be used to interface to the
DIMM serial-presence-detect port, if dynamic boot time determination of
SDRAM configuration is required.
Self-Refresh.
When the SDRAM is in Self-Refresh mode, the SDRAM’s internal timer
initiates Auto-Refresh cycles periodically, without external control input.
The SDC must issue a series of commands including the Self-Refresh
command to put the SDRAM into this low power mode, and it must issue
another series of commands to exit Self-Refresh mode. Entering
Self-Refresh mode is programmable in the SDRAM Memory Global Con-
trol register (
EBIU_SDGCTL
) and any access to the SDRAM address space
causes the SDC to exit the SDRAM from Self-Refresh mode. See “Enter-
ing and Exiting Self-Refresh Mode (SRFS)” on page 18-44 .
t
RAS
.
Required delay between issuing a Bank Activate command and issuing a
Precharge command, and between the Self-Refresh command and the exit
from Self-Refresh. The
TRAS
bit field in the SDRAM Memory Global
Control register (
EBIU_SDGCTL
) is 4 bits wide and can be programmed to
be 1 to 15 clock cycles long. “Selecting the Bank Activate Command
Delay (TRAS)” on page 18-47 .