Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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G-28 ADSP-BF535 Blackfin Processor Hardware Reference
t
RP
.
Required delay between issuing a Precharge command and:
• issuing a Bank Activate command
• issuing an Auto-Refresh command
• issuing a Self-Refresh command
The
TRP
bit field in the SDRAM Memory Global Control register
(
EBIU_SDGCTL
) is 3 bits wide and can be programmed to be 1 to 7 clock
cycles long. “Selecting the Precharge Delay (TRP)” on page 18-48 .
t
RCD
.
Required delay between a Bank Activate command and the start of the
first Read or Write command. The
TRCD
bit field in the SDRAM Memory
Global Control register (
EBIU_SDGCTL
) is 3 bits wide and can be pro-
grammed to be from 1 to 7 clock cycles long.
t
WR
.
Required delay between a Write command (driving write data) and a Pre-
charge command. The
TWR
bit field in the SDRAM Memory Global
Control register (
EBIU_SDGCTL
) is 2 bits wide and can be programmed to
be from 1 to 3 clock cycles long.
t
RC
.
Required delay between issuing successive Bank Activate commands to the
same SDRAM internal bank. This delay is not directly programmable.
The t
RC
delay must be satisfied by programming the
TRAS
and
TRP
fields
to ensure that t
RAS
+ t
RP

t
RC
.