Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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UART1 Controller Registers
B-8 ADSP-BF535 Blackfin Processor Hardware Reference
UART1 Controller Registers
Table B-7 lists the MMR assignments for the UART1 Controller registers
(0xFFC0 1C00–0xFFC0 1FFF).
0xFFC0 1B0C UART0_DESCR_RDY_TX “UARTx Transmit DMA Descriptor
Ready Registers
(UARTx_DESCR_RDY_TX)” on
page 12-34
0xFFC0 1B0E UART0_IRQSTAT_TX “UARTx Transmit DMA IRQ Status
Registers (UARTx_IRQSTAT_TX)”
on page 12-35
Table B-7. UART1 Controller Registers
Memory-Mapped
Address Register Name See Section
0xFFC0 1C00 UART1_THR “UARTx Transmit Holding Regis-
ters (UARTx_THR)” on page 12-5
0xFFC0 1C00 UART1_RBR “UARTx Receive Buffer Registers
(UARTx_RBR)” on page 12-6
0xFFC0 1C00 UART1_DLL “UARTx Divisor Latch Registers
(UARTx_DLL, UARTx_DLH)” on
page 12-10
0xFFC0 1C02 UART1_DLH “UARTx Divisor Latch Registers
(UARTx_DLL, UARTx_DLH)” on
page 12-10
0xFFC0 1C02 UART1_IER “UARTx Interrupt Enable Registers
(UARTx_IER)” on page 12-7
0xFFC0 1C04 UART1_IIR “UARTx Interrupt Identification
Registers (UARTx_IIR)” on
page 12-9
Table B-6. UART0 Controller Registers (Cont’d)
Memory-Mapped
Address Register Name See Section