Analog Devices ADSP-BF535 Blackfin, Hardware Reference Manual

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ADSP-BF535 Blackfin Processor Hardware Reference 1-5
Introduction
Blackfins support a modified Harvard architecture in combination with a
hierarchical memory structure. Level 1 (L1) memories operate at the full
processor speed. On-chip and off-chip Level 2 (L2) memories can take
multiple processor cycles to access. At the L1 level, the instruction mem-
ory holds instructions only. The two data memories hold data, and a
dedicated scratchpad data memory stores stack and local variable informa-
tion. At the L2 level, there is a single unified memory space, holding both
instructions and data.
In addition, the L1 instruction memory and L1 data memories may be
configured as either static RAMs (SRAMs) or caches. The Memory Man-
agement unit (MMU) provides memory protection for individual tasks
that may be operating on the core and may protect system registers from
unintended access.
The architecture provides three modes of operation: User, Supervisor, and
Emulation. User mode has restricted access to a subset of system resources,
thus providing a protected software environment. Supervisor and Emula-
tion modes have unrestricted access to the system and core resources.
The Blackfin instruction set is optimized so that 16-bit opcodes represent
the most frequently used instructions. Complex DSP instructions are
encoded into 32-bit opcodes as multifunction instructions. Blackfins sup-
port a limited multi-issue capability, where a 32-bit instruction can be
issued in parallel to two 16-bit instructions. This allows the programmer
to use many of the core resources in a single instruction cycle.
The Blackfin assembly language uses an algebraic syntax. The architecture
is optimized for use with a C/C++ compiler.
Memory Architecture
The Blackfin architecture structures memory as a single, unified 4 Gbyte
address space using 32-bit addresses. All resources, including internal
memory, external memory, PCI address spaces, and I/O control registers